1. Field of the Invention
The present invention relates to semiconductor packaging and methods for packaging semiconductor devices. More particularly, the invention relates to a PoP (package-on-package) using electrically insulating material between the packages and thermal compression bonding to couple the packages.
2. Description of Related Art
Package-on-package (“PoP”) technology has become increasingly popular as the demand for lower cost, higher performance, increased integrated circuit density, and increased package density continues in the semiconductor industry. As the push for smaller and smaller packages increases, the integration of die and package (e.g., “pre-stacking” or the integration of system on a chip (“SoC”) technology with memory technology) allows for thinner packages. Such pre-stacking has become a critical component for thin and fine pitch PoP packages.
A problem that arises with thin and fine pitch PoP packages is the potential for warping as the pitch is reduced between terminals (e.g., balls such as solder balls) on either the top package or the bottom package in the PoP package. The warping problem in the PoP structure may be further increased with the use of thin or coreless substrates in the packages. The top package and the bottom package in a PoP structure may have different warpage behavior because of differences in the materials used and/or differences in their structures. The differences in warpage behavior may be caused by differences in the characteristics of materials used in the packages that cause the packages to expand/contract at different rates.
The differences in warpage behavior between the top and bottom packages may cause yield loss in the solder joints coupling the packages (e.g., the connections between solder balls on the top package and landing pads on the bottom package). A large fraction of PoP structures may be thrown away (rejected) because of stringent warpage specifications placed on the top and bottom packages. The rejected PoP structures contribute to low pre-stack yield, wasted materials, and increased manufacturing costs.